Digital control circuit for serial UART transmissions

ABSTRACT

A digital control circuit enables/disables the feedback of serial transmissions of an UART receive signal when the G-LINK output port is short circuited in a particular operational mode. In a conventional operational mode, the digital control circuit monitors the state of the UART&#39;s Tx output and during an UART transmission, the Rx line normally is used for statistics feedback to set to a high state and eliminate unnecessary or unwarranted UART interrupts generated by the G-LINK circuit. The digital control circuit thus enables the G-LINK signal feedback to the UART when required, thereby maintaining a functionality to identify the unit&#39;s operational mode and allows the serial ports of the G-LINK to be configured and utilized during conventional operational modes.

This application claims the benefit, under 35 U.S.C. § 365 ofInternational Application PCT/US03/10400, filed Apr. 4, 2003, which waspublished in accordance with PCT Article 21(2) on Oct. 23, 2003 inEnglish and which claims the benefit of U.S. Provisional patentapplication No. 60/371,983, filed Apr. 12, 2002.

FIELD OF THE INVENTION

The present invention relates to control circuits in television set-topboxes, and more particularly, to a feedback control circuit.

BACKGROUND

In order to achieve high-speed packet transmission, a gigabit ratetransmit/receive chip set (transceiver) must be employed. One suchtransceiver is a device sold by the Hewlett Packard Companyheadquartered in Palo Alto, Calif., USA, which makes and sells atransmitter designated as the HDMP-1022 transmitter and a receiverdesignated as the HDMP-1024 receiver. The HDMP-1022 transmitter andHDMP-1024 receiver chip set is described in detail in a 40-pagePreliminary Technical Data sheet dated August 1996, distributed byHewlett Packard and, at present, has been available on its Internetwebsite. This data sheet shows how the HDMP-1022 transmitter and theHDMP-1024 receiver can be utilized as a gigabit, or G-LINK™ controller,to provide transmit and receive G-LINK serial interface operations. TheG-LINK of the present invention is an upgraded G-LINK II.

An application of a G-LINK controller is shown in FIG. 1, which can beused in a set-top box. In the figure, a G-LINK circuit 10 serves as aserial interface circuit for coupling a conventional universalasynchronous receiver-transmitter (UART) circuit 12 to a G-LINK serialport 14 for a plurality of purposes, such as providing the UART 12 witha signal path and controls for converting from full duplex to halfduplex communication to and from the G-LINK serial port 14. In addition,the G-LINK circuit 10 may relay infrared (IR) signals received from IRblaster source 20 via data line 21 for the G-LINK serial port 14 todrive an IR blaster (not shown).

All the components in FIG. 1 are controllable by an operating system(not shown) and the UART 12 is defined as a COM port. As such, when theUART 12 receives a signal, it generates an interrupt signal to beprocessed by the operating system. In one mode of operation such as in aconfiguration test mode wherein the configuration of the system istested, the G-LINK circuit 10 forwards a test signal from the G-LINKserial port 14 to the UART 12. Under this mode of operation, the UART 12should receive the test signal and generate interrupts accordingly.However, in another mode of operation, such as in a demonstration modewherein a user is educated on the use and capabilities of the system,the G-LINK circuit 10 unnecessarily transmits signals it receives fromthe UART 12 back to the UART 12. This unnecessary feedback causes theUART 12 to generate unnecessary interrupts to be served by the operatingsystem. The processing of these unnecessary interrupts may degrade theperformance of the set-top box. Thus, there is a need to control thecommunication between the G-LINK circuit and the UART 12.

SUMMARY OF THE INVENTION

According to the principles of the invention, a digital control circuit(DCC) enables/disables signals transmitted from a second circuit (suchas a G-LINK circuit) to an input/output device (such as an universalasynchronous receiver/transmitter (UART)). In addition to transmittingsignals to the input/output device, the second circuit also receivessignals transmitted from the input/output device. The DCC may controlthe signals transmitted from the second circuit according to the signalstransmitted by the input/output device to the second circuit. Forexample, when the input/output device is transmitting signals to thesecond circuit, the DCC inhibits signals transmitted from the secondcircuit to the input/output device. This way, the input/output devicedoes not receive any signals from the second device and thus does notgenerate interrupts to a central processing unit (CPU).

In one embodiment, the second circuit is a G-LINK circuit having abi-directional line coupled to a G-LINK port, and the input/outputdevice is a UART. When the G-LINK port is short-circuited in aparticular operational mode, the DCC prevents signal transmissions fromthe G-LINK circuit to the UART. In another operational mode, the DCCmonitors the state of the UART's output and during UART transmission,the DCC sets a high state on the receive line of the UART, indicating noincoming signals and thus preventing unnecessary or unwarranted UARTinterrupts from being generated by signals coming from the G-LINKcircuit. In yet another operation mode, the DCC allows free flow ofsignals to be transmitted from the G-LINK circuit to the UART. The DCCthus enables the G-LINK signal feedback to the UART when required.

BRIEF DESCRIPTION OF THE DRAWINGS

The teachings of the present invention can be readily understood byconsidering the following detailed description in conjunction with theaccompanying drawings, in which:

FIG. 1 depicts a prior art circuit arrangement using a G-LINK circuit, aG-LINK serial port, a UART, and an IR blaster source in a set-top box;

FIG. 2 depicts a circuit arrangement according to the principles of theinvention for controlling communications between the G-LINK circuittransmit line and the UART receive line;

FIGS. 3A and 3B illustrate an exemplary digital control circuit used inthe circuit arrangement shown in FIG. 2 and the setup arrangements fordifferent modes of operation;

FIG. 4 illustrates a flowchart showing the steps for entering thedemonstration mode under the control of the CPU and the operatingsystem; and

FIG. 5 illustrates a flowchart for a method for controlling transmissionfrom a serial interface circuit to a receiver-transmitter circuitaccording to the mode of operation.

To facilitate understanding, identical reference numerals have beenused, where possible, to designate identical elements that are common tothe figures.

DETAILED DESCRIPTION

FIG. 2 illustrates an exemplary circuit arrangement according to theprinciples of the invention. A G-LINK circuit 10 serves as a serialinterface circuit for coupling a conventional universal asynchronousreceiver-transmitter (UART) circuit 12, e.g., a portion of a TL811integrated circuit made by TeraLogic Inc. headquartered in Mountain ViewCalif., USA, to a G-LINK serial port 14 for a plurality of purposes,e.g., to provide the UART 12 with a signal path and controls forconverting from full duplex to half duplex communication to and fromG-LINK serial port 14, or to provide a signal path directly from theUART 12 to the G-LINK serial port 14 for full duplex communications, forfurther design improvements or for troubleshooting purposes. A digitalcontrol circuit (DCC) 22 is disposed between an output line (GLNK_Rx 18)of the G-LINK circuit 10 and a receive (input) line (UART_Rx 23) of theUART 12 for controlling the signals transmitted from the G-LINK circuit10 to the UART 12 according to the activity present at GLNK_Tx 16 (theoutput line of the UART 12 or the input line of G-LINK circuit 10) andother factors discussed below.

Additionally, the present arrangement is used for the G-LINK serial port14 to drive an infrared (IR) blaster (not shown) in response to an IRblaster source 20 via an IR blaster data line 21 coupled to G-LINKcircuit 10 as shown in FIG. 2. The IR blaster is an infrared lightemitting diode (LED), disposed outside of the set-top box, forcontrolling an external device (not shown) which can be remotelycontrollable by IR signals, e.g., a VCR, television receiver, DVDplayer, etc. The use of an IR blaster for such a purpose is known tothose skilled in the art. The IR blaster source 20 is driven by acomplex programmable logic device (CPLD) (not shown) and is discussedmore fully below.

The circuit arrangement in FIG. 2 can also be used in a manner wherepaging control commands can be transmitted from the UART 12 to G-LINKserial port via the G-LINK circuit 14 for controlling an external pagermodule to establish a connection with a paging service provider. Thiscircuit arrangement has been used in the ATC311 high definitiontelevisions provided by Thomson Inc., Indianapolis, Ind., USA.

The invention is particularly suitable for use in a set-top box (notshown) for a television receiver (not shown). Only those portions of theset-top box and/or the television receiver necessary for understandingthe present invention are further discussed below. For example, theset-top box has an operating system, which in the present case isWindows CE™, a product of the Microsoft Corp. headquartered in RedmondWash., USA, and a central processing unit (CPU) (not shown) both ofwhich control the UART 12, the G-LINK circuit 10 and the DCC 22discussed below. When the UART 12 receives a signal, the UART 12generates an interrupt signal, which normally requires the operatingsystem to jump to an interrupt handler to process the interrupt. Otherinput/output or receiver-transmitter devices such a universalsynchronous/asynchronous transmitter-receiver (USART) may be used inthis circuit arrangement as well.

The circuit arrangement in FIG. 2 operates under several modes ofoperation. In a configuration test mode of operation, the DCC 22 allowsall the signals transmitted from the G-LINK circuit 10 to be deliveredto the UART 12. In a demonstration mode, the DCC 22 disables any signalstransmitted from the G-LINK circuit 10 to the UART 12. The operatingsystem should not place the set-top box in the demonstration mode unlessthe operating system detects that the G-LINK serial port 14 isshort-circuited, which is an indication from a user that the user wantsthe set-top box to enter the demonstration mode. When the G-LINK serialport 14 is short-circuited, the G-LINK circuit 10 generally returns anysignals that it receives from the UART 12. Thus, to detect whether theG-LINK serial port is short-circuited, the operating system may placethe set-top box in the configuration test mode, send a test signal tothe G-LINK circuit 10 through the UART 12, and wait to see if the testsignal returns from the UART 12. If the test signal returns, theoperating system determines that the G-LINK serial port has beenshort-circuited and may proceed to place the set-top box in thedemonstration mode. Short-circuiting the G-LINK serial port 14 can beachieved by shorting the plug, thereby shorting the data signal line toground.

When the G-LINK serial port 14 is not short-circuited, the set-top boxnormally is operating under a default mode, in which a tester by usingtest equipment is able to send debug messages from the UART 12 to G_LINKserial port 14. Under the default mode of operation, the G-LINK circuit10 sends back signals it receives from the UART 12, which isunnecessary. To eliminate or mask interrupts generated by these returnedsignals, the DCC 22 monitors the state of the UART output line GLNK_Tx16 and during UART 12 transmission, the UART receive line UART_Rx 23, isset to a high state, indicating to the UART 12 that no signals have beenreceived and blocking the signals coming from the G-LINK circuit 10.

When the G-LINK serial port 14 is not short-circuited, the operatingsystem may also place the set-top box in an IR blaster mode. Under thismode, the G-LINK circuit 10 generally sends signals to the UART 12.These signals are unnecessary. As such, the DCC 22 disables any signalstransmitted from the G-LINK circuit 10 via GLNK_Rx 18 to the UART 12,again eliminating unnecessary interrupts.

The DCC hardware logic and control registers are shown in FIG. 3A. Thetable of FIG. 3B shows the logical behavior for the DCC 22 for eachcontrol register's setting and corresponding data inputs. In FIGS. 3Aand 3B, GLNK_Rx, GLNK_Tx, and UART_Rx represent logic (signal) states atGLNK_Rx 18, GLNK_Tx 16, and UART_Rx 23, respectively. FIG. 3A shows thatDCC 22 comprises five devices U1 through U5. U1 24 is a sequentiallyclocked flip-flop functioning as a latch, U2 26 and U3 28 comprisecommon low level logic gates, and U4 30 and U5 32 are common signalmultiplexers. The DCC 22 takes the following inputs to generate UART_Rx:GLNK_Tx, GLNK_Rx, register 4 bit 3, register 6 bit 2, and register 6 bit4. Registers 4 and 6 are included in a complex programmable logic device(CPLD) (not shown) and are set by the operating system. In the followingdiscussion, a logic value of 1 (high) generally means that no signalsare transmitted. For example, when GLNK_Tx has a logic value of 1, itgenerally means that the GLNK_Tx 16 line is idle, i.e., not transmittingor receiving.

U4 30 and U5 32 multiplexers provide the G-LINK circuit 10 with threesystems level operating modes. The simplest mode is the demonstrationmode (setup number 5 or mode 3 in FIG. 3B) where the output of U5 32 isat a logic high level—UART_Rx has a logic value of 1, i.e., the UART_Rx23 line is idle and thus the UART 12 does not receive any signal. Thismode is actuated when U5 32 has a control signal from the CPLD withregister 6 bit 4 being set to a logic level 1 as shown in the table ofFIG. 3B.

When register 6 bit 4 is set to a logic low level, the DCC 22 operatesin one of the other two modes, or one of setup numbers 1-4. The outputof U5 32 directly depends on the output of U4 30 according to FIG. 3B.U4 multiplexer is controlled by the logic level of CPLD register 6 bit2. When the logic level of CPLD register 6 bit 2 is high, the DCC 22operates under the configuration test mode or mode 2. In this case, theoutput of U4 30 is just the signals coming from GLNK_Rx 18. See FIG. 3A.As such, the output signals at UART_Rx 23 are the same as those comingfrom GLNK_Rx 18. Thus, the DCC 22 enables the free flow of signalstransmitted from the G-LINK circuit 10 to the UART 12. This is necessarybecause the test signals are generally transmitted through the G-LINKserial port 14 to the UART 12 to be processed by the operating system.

When CPLD register 6, bit 2 is set to a logic low level, the DCC 22operates under mode 1. The output of U4 30 directly depends on theoutput of U3 28, which is a NAND gate having three inputs: CPLD register14 bit 3, the signals coming from GLNK_Tx and the output signals from U226. U2 26 is an inverter for inverting signals coming from GLNK_Rx 18. Asignal from GLNK_Tx 16 is latched at U1 24 when the signal from theGLNK_Rx 18 is transitioning from a logic value of 1 to 0. This latchedstate of G-LINK-Tx 16 eliminates false logic transitions at the outputof U3 28 that may be due to phase or timing differences in the G-LINK_Rx18 and G-LINK_Tx 16 signals.

Under mode 1, when CPLD register 14 bit 3 is set to a logic value of 1,the DCC 22 is in default operating condition. The DCC in this defaultoperating condition checks whether the UART 12 is transmitting signalsto the G-LINK circuit 10. If the UART 12 is not transmitting, the DCC 22enables signals transmitted from the G-LINK circuit 10 to the UART 12.Otherwise, if the UART 12 is transmitting, the DCC 22 disables thesignals transmitted from the G-LINK circuit 10. In FIGS. 3A and 3B, whenthe signals from GLNK_Tx 16 have a logic value of 1 (no signals), theoutput of U3 28 is the output of U2 26 or the signals coming fromGLNK_Rx 18. In effect, the signals at UART_RX 23 are the same as thosecoming in at GLNK_Rx 18. On the other hand, if signals from GLNK_Tx 16have a logic value of 0 (the UART 12 is transmitting), the output of U328 has a logic value of 1. In effect, the signals at UART_Rx 23 are heldat a logic value of 1, disabling the transmission from the G-LINKcircuit 10 to the UART 12.

Under mode 1, if CPLD register 14 bit 3 is set to a logic value of 0,the IR blaster is active, i.e., the G-LINK circuit 10 is receiving IRsignals from the IR blaster source 20 and transmitting the IR signals toan external IR blaster via the G-LINK serial port 14. Under thissituation, the output of U3 28 has a logic value of 1, which causes thesignals at UART_Rx 23 to have a logic value of 1 as well, disabling thetransmission from the G-LINK circuit 10 to the UART 12.

It should be understood that the specific level signals from the CPLDand signal levels stated in FIG. 3B are specific to the operating systemused and associated circuitry, are exemplary and are presented to conveyan understanding of the operation to one skilled in the art. The CPLDand its respective registers form no part of the present invention.

When a shorting plug is inserted into the G-LINK serial port 14, thisshort-circuiting of the output is sensed and the system is placed in thedemonstration mode wherein the user is educated on the use andcapabilities of the system. It is of course understood that equivalentsof a shorting plug can be used, e.g., a front panel switch. This mode istypically utilized in a retail store for actuating a demonstration mode,and conforms to setup 5 of FIG. 3B. The operation of the demonstrationmode forms no part of the present invention.

FIG. 4 shows a flowchart of entering the demonstration mode of operationunder the control of the CPU and the operating system. When a usershort-circuits the G-LINK serial port 14, the user is instructing theset-top box to enter the demonstration mode. At 402 the UART isconfigured as a COM port, an option provided for by the operatingsystem. In the exemplary embodiment, the CPLD registers (not shown) areset at 404, where both bits 2 and 4 of the CPLD register 6 are set tozero, i.e., the set-top box is either in default or IR blaster mode. Theprocess continues through link 406 to node 408 for a determination ofwhether the IR blaster is active. In this embodiment and as shown inFIG. 3B, if register 14 bit 3 is zero, then the IR blaster mode isactive. If the IR blaster mode is active, there is a return to link 406.If “no”, there is a determination at 410 of whether the operating systemwants to test for whether the G-LINK serial port 14 is short-circuited(shown as “Test for DEMO PIN?”) for providing a demonstration, asdiscussed above. If “no”, there is a return to link 406. If “yes,” theCPLD registers are reset at 412, setting bit 2 of CPLD register 6 tologic 1 and bit 4 to a logic 0. This setting places the circuitarrangement in FIG. 3A in the configuration test mode. At 414, theoperating system determines whether the UART 12 input line, UART_Rx 23is at a logic zero, indicating that there is signals coming into theUART 12. As discussed above, when the serial port 14 is short-circuited,the G-LINK circuit 10 sends back any signals it receives from the UART12. Thus, when the operating system receives a signal it previouslysent, the operating system determines that the G-LINK serial port 14 isshort-circuited. If the decision block 414 returns “yes”, the CPLD isagain reset at 416 to place the circuit arrangement in FIG. 3A in thedemonstration mode. As shown in FIG. 3B, to set the circuit arrangementin the demonstrative mode, bit 2 of register 2 is set to logic 0 and bit4 is set to logic 1. The process then returns to link 406. If “no,” theprocess returns to 404, setting the circuit arrangement back to eitherthe default or the IR blaster alive mode.

FIG. 5 illustrates a method for controlling transmission from a serialinterface circuit such as the G-LINK circuit 10 in FIG. 2 to areceiver-transmitter circuit such as the UART 12 in FIG. 2 in a systemaccording to the mode of operation. At 510, the mode of the operation ofthe system is detected. The mode is determined at 520. If the mode is afirst mode such as the configuration test mode shown in FIG. 3B, allowthe serial interface circuit to transmit signals to thereceiver-transmitter circuit at 530. If the mode is in a second modesuch as the default mode shown in FIG. 3B, determine whether thereceiver-transmitter circuit is transmitting signals to the serialinterface circuit at 540. If the receiver-transmitter circuit istransmitting, prohibit the serial interface circuit to transmit signalsto the receiver-transmitter at 550. Otherwise, if thereceiver-transmitter is not transmitting, allow the serial interfacecircuit to transmit signals to the receiver-transmitter circuit. Asshown in FIG. 3A, the serial interface circuit may also include abidirectional line for interfacing with a serial port (such as theG-LINK serial port 14).

The examples given herein are presented to enable those skilled in theart to more clearly understand and practice the instant invention. Theexamples should not be considered as limitations upon the scope of theinvention, but as merely being illustrative and representative of theuse of the invention. Numerous modifications and alternative embodimentsof the invention will be apparent to those skilled in the art in view ofthe foregoing description. Accordingly, this description is to beconstrued as illustrative only and is for the purpose of teaching thoseskilled in the art the best mode of carrying out the invention and isnot intended to illustrate all possible forms thereof. It is alsounderstood that the words used are words of description, rather thanlimitation, and that details of the structure may be variedsubstantially without departing from the spirit of the invention and theexclusive use of all modifications which come within the scope of theappended claims is reserved.

1. A circuit arrangement comprising: a first circuit having an outputline and an input line; a second circuit having an input line forreceiving signals from the output line of the first circuit, and anoutput line for transmitting signals to the input line of the firstcircuit; a control circuit having input lines for receiving the signalsfrom the output lines of the first and second circuits, the controlcircuit inhibiting the signals transmitted from the output line of thesecond circuit to the input line of the first circuit when the firstcircuit is transmitting signals to the input line of the second circuitand thereby preventing the second circuit from re-transmitting thesignals received from the first circuit back to the first circuit andfurther preventing the first circuit from generating an interruptsignal; and wherein the circuit arrangement is included in a televisionreceiver.
 2. The circuit arrangement of claim 1, wherein the controlcircuit keeps the input line of the first circuit at a high state whenthe first circuit is transmitting signals to the input line of thesecond circuit.
 3. The circuit arrangement of claim 1 wherein the firstcircuit is a selected one of a Universal AsynchronousReceiver/Transmitter (UART) and a Universal Synchronous/AsynchronousReceiver/Transmitter (USART).
 4. The circuit arrangement of claim 3,wherein the second circuit is a G-Link circuit.
 5. The circuitarrangement of claim 1, wherein the second circuit further comprises abi-directional line.
 6. The circuit arrangement of claim 5, whereinshort-circuiting the bi-directional line initiates a demonstration mode.7. The circuit arrangement of claim 6 wherein the shorting circuiting isa short circuit to ground.
 8. The circuit arrangement of claim 1 whereinthe control circuit inhibits the signals transmitted from the outputline of the second circuit to the input line of the first circuit whenthe first circuit is transmitting signals to the input line of thesecond circuit during a first mode of operation and allows the secondcircuit to transmit signals to the first circuit during a second mode ofoperation.
 9. The circuit arrangement of claim 1, wherein signalstransmitted from the output line of the first circuit control anexternal pager module through the second circuit for connecting to apager service.
 10. The circuit arrangement of claim 1, wherein thesecond circuit further comprises a second input line for receiving IRsignals transmitted from an IR source and a second output line fortransmitting the IR signals for remotely controlling an external device.11. The circuit arrangement of claim 1, wherein the second circuitprovides feedback between the output line of the first circuit and theinput line of the first circuit.
 12. The circuit arrangement of claim 1wherein the control circuit inhibits the signals transmitted from theoutput line of the second circuit to the input line of the first circuitaccording to a mode of operation.
 13. a method for controllingcommunication from a serial interface circuit to a receiver-transmittercircuit in a system under control of a CPU and an operating system, themethod comprising the steps of: detecting a mode of operation of thesystem; when the mode is a first mode, allowing the serial interfacecircuit to transmit signals to the receiver-transmitter circuit whereinthe serial interface circuit corn rises a bi-directional line; and whenthe mode is a second mode, detecting whether the receiver-transmittercircuit is transmitting signals to the serial interface circuit, andwhen the receiver-transmitter circuit is transmitting signals to theserial interface circuit, prohibiting the serial interface circuit fromre-transmitting the signals received from the receiver-transmittercircuit back to the receiver-transmitter circuit and thereby preventingthe receiver-transmitter circuit from generating an interrupt signal;and wherein the method is performed in a television receiver.
 14. Themethod of claim 13 wherein the receiver-transmitter circuit is aselected one of a Universal Asynchronous Receiver/Transmitter (UART) anda Universal Synchronous/Asynchronous Receiver/Transmitter (USART). 15.The method of claim 13, wherein the serial interface circuit is a G-Linkcircuit.
 16. The method of claim 13, wherein short-circuiting thebi-directional line initiates a demonstration mode.
 17. the method ofclaim 16, wherein the shorting circuiting is a short circuit to ground.18. a circuit arrangement comprising: a first circuit having an outputline and an input line; a second circuit having an input line forreceiving signals from the output line of the first circuit, and anoutput line for transmitting signals to the input line of the firstcircuit, the second circuit further comprising a bi-directional line;and a control circuit having input lines for receiving the signals fromthe output lines of the first and second circuits, the control circuitinhibiting the signals transmitted from the output line of the secondcircuit to the input line of the first circuit when the first circuit istransmitting signals to the input line of the second circuit and therebypreventing the second circuit from re-transmitting the signals receivedfrom the first circuit back to the first circuit and further preventingthe first circuit from generating an interrupt signal; and wherein thecircuit arrangement is included in a television receiver.
 19. Thecircuit arrangement of claim 18, wherein short-circuiting thebi-directional line Initiates a demonstration mode.
 20. The circuitarrangement of claim 18, wherein the first circuit is one of a UniversalAsynchronous Receiver/Transmitter (UART) and a UniversalSynchronous/Asynchronous Receiver/Transmitter (USART).